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CBM2091
Datasheet
Chipsbank Microelectronics Co., Ltd.
No.201-205,2/F,Building No.4,Keji Central Road 2, Software Park,High-Tech Industrial Park,Shenzhen, P.R.China 518057 Tel: 0755-86169650-808 Fax: 0755-86169690 Email: info@chipsbank.com URL: http://www.chipsbank.com (c) 2007 Copyright Chipsbank Microelectronics Co., Ltd. All rights reserved.
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Contents
1 2 3 4
DESCRIPTION ........................................................................................................................................ 1 FEATURES .............................................................................................................................................. 1 BLOCK DIAGRAM ................................................................................................................................. 3 PIN ASSIGNMENT ................................................................................................................................. 4
4.1 TQFP48 (TOP SIDE) .............................................................................................................................. 4 4.2 LQFP64 (TOP SIDE) .............................................................................................................................. 5 5 6 PIN DESCRIPTION................................................................................................................................. 6 ELECTRICAL CHARACTERISTICS ................................................................................................. 10
6.1 ABSOLUTE MAXIMUM RATINGS .................................................................................................... 10 6.2 RECOMMENDED OPERATING CONDITIONS ............................................................................... 10 6.3 STATIC CHARACTERISTICS............................................................................................................. 10 6.4 DYNAMIC CHARACTERISTICS ........................................................................................................ 11 7 8 TYPICAL APPLICATION ..................................................................................................................... 13 MECHANICAL DIMENSIONS............................................................................................................. 14
8.1 48-PIN CBM2091 PACKAGE OUTLINE DIMENSION ................................................................... 14 8.2 64-PIN CBM2091 MODE PACKAGE OUTLINE DIMENSION ...................................................... 15 9 COPYRIGHT NOTICE.......................................................................................................................... 16
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1 Description
Fastest & Securest USB 2.0 Flash Disk Controller with dedicated 32-bit microprocessor
The CBM2091 is the USB 2.0 Flash Disk controller with the fastest transfer speed on the market. CBM2091 can reach theoretical flash access speed limit of over 32MByte/s for read and 20MByte/s for write. The on-the-fly ECC engine is capable of correcting up to 4bytes (32bits), detect 5 or more bytes errors per 528bytes page . For data security, CBM2091 is designed with both hardware and software data protection technology to prevent data corruption even if it is powered off or unplugged during data transfer. The CBM2091 supports all 8 bit and 16 bit NAND/MLC/AG-AND flash memory available in the market. New flash can be supported by software re-configuration. It also supports SPI NOR flash without extra components needed. The CBM2091 has both a) 5V to 3.3V LDO and b) power on reset circuits integrated. Thus greatly reduced BOM cost and eased layout burden. The CBM2091 runs smoothly with all available hosts and PC platforms. Complied with USB specification rev. 2.0, the CBM2091 can be supported without additional driver under Win XP, Win 2000, Windows Me, Mac OS and Linux OS. With device driver installed, it can support Win 98/98SE as well. Comprehensive applications, such as PC boot up, disk partitions, password check for security disk, are available as part of our standard mass production software package. The CBM2091 is available in 48-pin TQFP and 64-pin LQFP package, which are thinnest and smallest on the market. The 48-pin CBM2091 supports up to 4 flash chips and the 64-pin CBM2091 supports up to 8 flash chips. Customers can choose different packages to meet their design requirement.
2 Features
USB Interface High-speed USB 2.0 interface; Fastest data transfer rate on the market Dual-channel mode: 32MB/s for Read, 20MB/s for Write Single-channel mode: 17MB/s for Read, 16MB/s for Write Fastest file copy rate on the market. On-the-fly ECC built-in Hardware enhances reliability
ECC for Binary NAND flash: ECC for MLC NAND flash: ECC for AG-AND flash:
4-32 bit/page (1 page = 528 bytes) 8-32 bit/page 8-32 bit/page
Special wheel leveling algorithm to improve the flash life-time Hardware & Software Data Protection Technology
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Prevent data corruption even if it is powered off or unplugged during data transfer.
NAND, AG-AND & MLC Flash Interface Support 4k page flash parallel mode. Support 8-bit and 16-bit Samsung SLC and MLC NAND flash. Support 8-bit and 16-bit Toshiba SLC and MLC NAND flash. Support 8-bit and 16-bit Hynix SLC and MLC NAND flash. Support 8-bit and 16-bit ST Microelectronics SLC and MLC NAND flash. Support 8-bit and 16-bit Micron/IM SLC and MLC NAND flash. Support 8-bit and 16-bit Infenion SLC and MLC NAND flash. Support 8-bit and 16-bit Sandisk SLC and MLC NAND flash. Support Renesas AG-AND and AND flash memories Support Actrans flash memories Support SPI Nor flash without extra components needed Software configuration to support various new flash memories Supports up to 8 flash chips. Proprietary 32-bit CISC microprocessor feature Proprietary 32-bit CISC processor for USB protocol processing and flash access. Single cycle instruction period Integrated 5v to 3.3v voltage regulator Disk partitions and password check for security disk available PC boot up as USB Zip Disk, USB Hard Disk or CDROM Auto run function Low power dissipation Operating current 50mA (Bus power compatible) Leading 0.18um CMOS technology 48-pin TQFP /64-pin LQFP package 48-pin CBM2091 supports up to 4 Flash Chips 64-pin CBM2091 supports up to 8 Flash Chips Windows, Mac and Linux compatible
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3 Block Diagram
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4 Pin Assignment
4.1 TQFP48 (Top Side)
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4.2 LQFP64 (Top Side)
FDATA2_0
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
FDATA2_1 FDATA2_2 FDATA0_0 FDATA0_1 FDATA0_2 FDATA2_3 FDATA0_3 FDATA2_4 FDATA0_4 FDATA2_5 FDATA0_5 FDATA2_6 FDATA0_6 FDATA2_7 FDATA0_7 RST_OUT
49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9
33 32 31 30 29 28 27 26 25 24
FDATA3_0
CLKOFF
FCEN1
FCEN2
FCEN3
FCEN0
VDD33
FRDN
FCLE
FRB1
FALE
WP
FWRN
FRB0
X_LED
FDATA1_0 FDATA3_1 FDATA3_2 FDATA1_1 FDATA1_2 FDATA3_3 FDATA1_3 FDATA3_4 FDATA1_4 FDATA3_5 FDATA1_5 VSS FDATA3_6 FDATA1_6 FDATA3_7 FDATA1_7
64PIN LQFP 10mmA 10mmA 1.4mm
23 22 21 20 19 18 17
RESET
VDD33
VDD50
VDD33
VDD18
VS33A XI
DM
XO
VSSU
TEST_MODE
VDDU
VSS
VPP
REXT
DP
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5 Pin Description
Brief CBM2091 pin functions are shown in the following tables.
I: O: I/O : PWR : GND: PU: PD:
Input signal Output signal Bi-direction signal Power signal Ground signal pull up pull down
CBM2091
LQFP64 Pin No.
3 4 5 6 7 8 9 10 2 12 13 14 15 16 17
LQFP64 / TQFP48 Pin Description
TQFP48 Pin No.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Pin Name
VDD50 VDD33 VDD18 VPP REXT VD33 DP DM VSS XI XO VSSU VDDU TEST_MODE FDATA1_7 GPIO15
Type
PWR PWR PWR I I PWR I/O I/O GND I O GND PWR I PD I/O PU
Description
Regulator5V Power Input Regulator 3.3V Power OUT Regulator 1.8V Out Inner Programme Resister for current
Connect External reference Padring 3.3V Power USB Data D+ USB Data D-
Padring 3.3V / Logic 1.8V Ground Crystal Input (12 MHz) Crystal Output Analog 1.8V Ground Analog 1.8V Power Test Mode Enable Pin When high , test mode When low , normal mode Group 1 Flash Data Bus - bit 7 General I/O port 15 When select spi mode ,as spi chip select .
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19
16
FDATA1_6 GPIO14
I/O PU
(configure as GPIO and clear pin_64( detail in spi_ctl[13] .when select master mode , configure output , otherwise, configure as input.). Group 1 Flash Data Bus - bit 6 General I/O port 14 When select spi mode, as clock out support ligh-tun sensor (configure as GPIO and clear pin_64( detail in spi_ctl[13] .when select ligh-tun mode , configure output). Padring 3.3V / Logic 1.8V Ground Group 1 Flash Data Bus - bit 5 General I/O port 13 Group 1 Flash Data Bus - bit 4 General I/O port 12 Group 1 Flash Data Bus - bit 3 General I/O port 11 Group 1 Flash Data Bus - bit 2 General I/O port 10 Group 1 Flash Data Bus - bit 1 General I/O port 9 Group 1 Flash Data Bus - bit 0 General I/O port 8 When TEST_MODE =1, as scan clock input. When TEST_MODE =0, as LED Indication Group Group Flash Write Enable (active low) Flash Address Latch Enable
21 22 24 26 28 29 32 34 35 36 37 38 39 40 41 42
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
VSS FDATA1_5 GPIO13 FDATA1_4 GPIO12 FDATA1_3 GPIO11 FDATA1_2 GPIO10 FDATA1_1 GPIO9 FDATA1_0 GPIO8 X_LED FWRN FALE WP FCLE VDD33 CLKOFF FCEN0 FRDN
GND I/O PU I/O PU I/O PU I/O PU I/O PU I/O PU I/O O O I O PWR I PD O O
Write Protect Switch Input Group Flash Command Latch Enable
Padring 3.3V Power Clock input switch. external test clock. CLK_OFF=1, select
Flash Chip Enable - Chip 0 (active low) Group Flash Read Enable (active low)
43
33
FRB1 /SYNC_F /INTR
I
44
34
/SCK(I2c) /MOSO FCEN3
O
Group Flash Ready_Busy 1, when select spi mode ,as light-tun frame sync signal. 2, when select flash_rb1 mode, as Group Flash Ready_Busy1 signal input(detail in soft_flag [30]). 3, when select intr mode, as external interrupt input signal(detail in soft_flag [30]). 1, When select test-mode, as scan-chain output 2, When select i2c , as sck
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45
35
FCEN2 /MISI
I/O PU
46
36
X_CLK_OUT /FCEN1 /MCLK_OUT /SCLK
I/O PU
3, When select spi_en, as master/slave output data 4, When select chip select2/3 mode, as CE3 output 1, When select test_mode, As scan-chain input 2, when select chip select2/3 mode, as CE2 output .(active when disable test_mode) 3, When deselect test_mod and chip-select2/3 mode , as spi master/slave data input .at same time, need set spi_en bit 1, When select clock input mode ( X_CLK_OFF =1 or select spi slave mode), (1), X_CLK_OFF=1, as external input test clock. (2), select spi slave mode , as spi slave SCLK input 2, When select chip select1 mode or spi master mode, as output. ( only active when X_CLK_OFF =0 or de-slect spi slve mode) (1), select spi master mode, as spi master clock output (2), select chip select1 mode (detail in soft_flag [30]), as CE1 output (3), otherwise, as normal clock_out ,which defined at config_r[20]. Group Flash Ready_Busy0 Group 0 Flash Data Bus - bit 0 General I/O port 0 Group 0 Flash Data Bus - bit 1 General I/O port 1 Group 0 Flash Data Bus - bit 2 General I/O port 2 Group 0 Flash Data Bus - bit 3 General I/O port 3 Group 0 Flash Data Bus - bit 4 General I/O port 4 Group 0 Flash Data Bus - bit 5 General I/O port 5 Group 0 Flash Data Bus - bit 6 General I/O port 6 Group 0 Flash Data Bus - bit 7 General I/O port 7 Chip reset output/ External device reset signal Low active pulse output Should connect with RESET pad Reset Sign (active low) Analog 3.3V Ground Group 2 Flash Data Bus - bit 0 General I/O port
8
48 51 52 53 55 57 59 61 63 64 1 8 47
37 38 39 40 41 42 43 44 45 46 47 48
FRB0 FDATA0_0 GPIO0 FDATA0_1 GPIO1 FDATA0_2 GPIO2 FDATA0_3 GPIO3 FDATA0_4 GPIO4 FDATA0_5 GPIO5 FDATA0_6 GPIO6 FDATA0_7 GPIO7 RST_OUT RESET VS33A FDATA2_0
I I/O PU I/O PU I/O PU I/O PU I/O PU I/O PU I/O PU I/O PU O I GND I/O PU
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49 50 54 56 58 60 62 33 31 30 27 25 23
FDATA2_1 FDATA2_2 FDATA2_3 FDATA2_4 FDATA2_5 FDATA2_6 FDATA2_7 FDATA3_0 FDATA3_1 FDATA3_2 FDATA3_3 FDATA3_4 FDATA3_5
I/O PU I/O PU I/O PU I/O PU I/O PU I/O PU I/O PU I/O PU I/O PU I/O PU I/O PU I/O PU I/O PU I/O PU
20
FDATA3_6
18
FDATA3_7
I/O PU
Group2 Flash Data Bus - bit 1 General I/O port Group 2 Flash Data Bus - bit 2 General I/O port Group 2 Flash Data Bus - bit 3 General I/O port Group 2 Flash Data Bus - bit 4 General I/O port Group2 Flash Data Bus - bit 5 General I/O port Group 2 Flash Data Bus - bit 6 General I/O port Group 2 Flash Data Bus - bit 7 General I/O port Group 3 Flash Data Bus - bit 0 General I/O port Group 3 Flash Data Bus - bit 1 General I/O port Group 3 Flash Data Bus - bit 2 General I/O port Group 3 Flash Data Bus - bit 3 General I/O port Group 3 Flash Data Bus - bit 4 General I/O port Group 3 Flash Data Bus - bit 5 General I/O port Group3 Flash Data Bus - bit 6 General I/O port When select spi mode, as clock out support ligh-tun sensor (configure as GPIO and set pin_64( detail in spi_ctl[13] .when select ligh-tun mode , configure output). Group 3 Flash Data Bus - bit 7 General I/O port When select spi mode ,as spi chip select . (configure as GPIO and set pin_64( detail in spi_ctl[13] .when select master mode , configure output , otherwise, configure as input.).
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6 Electrical Characteristics
6.1 Absolute maximum ratings
In accordance with the Absolute Maximum Rating System (IEC 60134).
symbol
VCCA VCCD VI Vesd Tstg
parameter
analog supply voltage digital supply voltage input voltage electrostatic discharge voltage[1] storage temperature ILI < 1A
conditions
min
-0.5 -0.5 -0.5
max
5.5 4.5 5.5 +4000
unit
v v v v
DP, DM and GND pins other pins
-4000 -2000 -40
+2000 +125
ae
[1] Equivalent to discharging a 100 pF capacitor via a 1.5 k
resistor (Human Body Model).
6.2 Recommended operating conditions
symbol
VCCA VCCD VI VI(AI/O) Tamb
Parameter
analog supply voltage digital supply voltage input voltage input voltage on analog I/O pins DP DM ambient temperature
conditions
min
3.0 3.0 0
Typ
3.3 3.3 3.3 400 -
max
3.6 3.6 VCCD 3.6 +70
Unit
V V V V mV
Low/Full speed High speed
0 0 0
ae
6.3 Static characteristics
All parameters are measured at VCCA = VCCD = 3.0 to 3.6 V; VAGND = VDGND = 0 V; Tamb = 40 to 85 ae ; symbol Parameter Conditions min Typ max Unit operating supply current suspend supply current Full-speed transmitting and receiving; high-speed transmitting and receiving in suspend mode 29.5 50 500 mA
ICC ICC(susp)
uA
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6.4 Dynamic characteristics
All parameters are measured at VCCA = VCCD = 3.0 to 3.6 V; VAGND = VDGND = 0 V; Tamb = 40 to 85 ae ;
symbol
Ts(FDATA*) Th(FDATA*) Ts (FCLE*) Th (FCLE*) Ts (FALE*) Th (FALE*) Ts (FCEN*) Tpw (FWRN*) Thh (FWRN*) Ta(FDATA*) Tpw (FRDN*) Thh (FRDN*)
Parameter
FDATA* setup time relative to rising FWRN* edge FDATA* hold time relative to falling FWRN* edge FCLE* setup time relative to falling FWRN* edge FCLE* hold time relative to rising FWRN* edge FALE* setup time relative to falling FWRN* edge FALE* hold time relative to rising FWRN* edge FCEN* setup time relative to falling FWRN* edge FWRN* Pulse Width FWRN* high hold time FDATA* access time relative to falling FRDN* edge FWRN* Pulse Width FWRN* high hold time
conditions
min
-
Typ
33 33 33 33 33 33 99 33 33 33 33
max
40 -
Unit
ns ns ns ns ns ns ns ns ns ns ns ns
Timing diagram for Writing of Data
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Timing diagram for Reading of Data
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7 Typical Application
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8 Mechanical Dimensions
8.1 48-Pin CBM2091 Package Outline Dimension
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8.2 64-Pin CBM2091 Mode Package Outline Dimension
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9 Copyright Notice
Copyright 2004-2007 by Chipsbank Microelectronics Co. Ltd. All Rights Reserved.
Right to make changes --Chipsbank Microelectronics Co., Ltd reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. The information contained in this manual is provided for the general use by our customers. Our customers should be aware that the personal computer field is the subject of many patents. Our customers should ensure that they take appropriate action so that their use of our products does not infringe upon any patents. It is the policy of Chipsbank Microelectronics Co., Ltd. to respect the valid patent rights of third parties and not to infringe upon or assist others to infringe upon such rights.
This manual is copyrighted by Chipsbank Microelectronics Co., Ltd. You may not reproduce, transmit, transcribe, store in a retrieval system, or translate into any language, in any form or by any means, electronic, mechanical, magnetic, optical, chemical, manual, or otherwise, any part of this publication without the expressly written permission from Chipsbank Microelectronics Co., Ltd.
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